I would be grateful if someone could explain the KT/C noise (input referred) contribution of Sampling Capacitor (CS) and feedback capacitor (CF) for the standard two capacitor S/H implementation (not the flip around architecture).
I did not remake the derivation but the path is the following:
Have a RC low pass filter. The R is the noise source with 4kT*R. The RC filters so that the power noise density get filtered by 1/(1+omega^2). If you integrate that up to infinity over frequency you get the expression above.
the noise contribution from the sampling capacitor is 2*k*T/Cs, where two times are from sampling phase and integrating phase. the noise contribution from feedback capacitor is 2*k*T*Cf/Cs² due to capacitance divider.
I have an amplifier circuit. It is not an integrator. In phase 1, the capacitor CS samples the input via a switch. In phase 2, the charge is transfered to another capacitor CF (feedback capacitor). This capacitor, along with the op-amp, hold the charge.
Please have a look at the image and suggest your views on the KT/C noise.
Thanks for your response. I agree with you that the KT/C noise should equal "KT/Cs".
I am slightly confused about the KT/C noise presented in the following document (page 242). Please note that this is a different SH architecture (flip-around).
**broken link removed**
The figure referred to in this analysis is as below:
If time permits, please have a look and let me know the reason of including CGS (parasitic gate to source capacitance of the op-amp input transistors) in noise calculation.