switch capacitor integrator

[tanuki]

I think you need to change your gate signals. M5 and M6 share the same gate signal and M2 and M3. During switching both of these pairs will conduct at the same time ("cross-conduct", "shoot through", etc.). Setup the phase clocks so there there is no overlap (suggestion: buffer using a SR flip flop, made of cross coupled nor gates.).

Also the opamp needs to be fast enough to reset the "-" node to zero (virtual ground) well before the next phase starts. On the other side of speed, you might also put a resistor in series with the opamp output to limit the charge transfer current current, so that the opamp doesn't go into short circuit limiting. In an actual circuit, the opamp voltages sources will have some impedance, therefore decouple the supply carefully and added ferrite beads, etc. You want to adjust the current limiting resistor so that on the largest input the opamp just manages to reset the "-" node to 99% (or as you like) just as the transfer phase ends.

Once you get the basic circuit working ... add in the parasitic elements too ... considering these elements is where your design skills will improve most.

 

[xdy83]

2) For your clock stimulus, make sure you are using 2 phase non-overlapping clocks.

this is the point

 

[lovexxnu]

the key is the clock and switches, I think
non-overlapped clock must be assured, and transit gate should be applied.

ideal op means the input impedance is infinite, but real is not.
so some of the real effects will not appear in ideal op.

 

[icehot]

Agree with dkace except that:
"2.Glitches will definite be away if you use dummy switches of equal size on the two sides of each switch"

I think the dummy switches have to be the half size of the two sides of each switch.

 

[yezeg]

The ideal opa is work well.I thinK the proble is OPA but not the switch or capacitor .

Tell us the frequency if switch and the OPA's gainband and settingtime!
Maybe the opa is not satable ,what is the PM?