How about you go and ask Mr. Rules Deck what the error means?
You haven't even said what foundry (who writes the rules) or
flow (rules for what?).
You could have a true open or short. You could have made the
mistake of using a special metal layer/purpose (some kits require
that (say) vdd! routes are only on vdd_met{1,2,3,4,5,6}/drawing
and vss! must be on vss_met{1,2,3,4,5,6}/drawing and no signal
is allowed on either (this greatly eases shorts location, if it is
implemented and followed). But this scheme ought to show up
in DRC, not just as late as LVS/extract.
At any rate the error has a particular reason and behind it a
specific logic, and you could find the snippet simply enough
by rules file text-search and its meaning, by inspection.