rhee high performance charge pumps
You can read these papers as reference.Hope it will be help you.
[1].J.Maneatis et al.,”Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL,”IEEE J.Solid-State Circuits,vol.31, pp.1795-1803,Nov.2003.
[2].Ian A.Young,”A PLL Clock Gernerator with 5 to 110 MHz of Lock Range for Microprocessors,”IEEE J.Solid-State Circuits,vol.27, pp.1599-1607,Nov.1992.
[3].L.Dai and R.Harjani,”CMOS Switched-Op-Amp-Based Sample-and-Hold Circuit,” IEEE J.Solid-State Circuits, vol.35,No.1, pp.109-113,Jan.2000.
[4].Mohamad El-Hage and Fei Yuan,”Architectures and Design Considerations of CMOS Charge Pumps for Phase-Locked Loops”
[5].R.C.chang and L.C.Kuo,”A new Low-Voltage Charge Pump Circuit for PLL”,IEEE International Symposium of Circuits and Systems ISCAS, Switzerland, pp.701-703, May 2-5,2000.
[6].J.Maneatis,”Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,”IEEE J.Solid-State Circuits, vol.31, No.11,Nov.1996.
[7].W.Rhee,”Design of High-Performance CMOS Charge-Pumps in Phase-Locked Loop,”in Proc.ISCAS,vol.1, pp545-548,1999.
[8].Esdras Juarez-Hernandes and Alejandro Diazsanchez,”A Novel CMOS Charge-Pump Circuit with Positive Feedback for PLL Applications,”in Proc.ICECS, vol349-352, 2001.
[9].Jae-Shin Lee et al.,”A Charge Pump with Perfect Current Matching Characteristics in Phase-Locked Loops,” in Electronics Letters,vol.36,pp.1907-1908,9 nov.2000.
girih192002 said:
Hello,
Do me a favor? I am designing Charge pump & PFD for PLL 500 to 1000 MHz Frequency range and i need 0.4 to 1.5 V tunning voltage to get generate from charge pump for VCO. Could you guys provide me some good papers, thesis or technical material or link for ?
I will very thankful of you....