jayh
Newbie level 6
hi
i don't know much about mix signal simulation(only experience about digital ASIC).
a SOC design with digital logic circuit and analog IP. a plan to do a mix signal simulation.
digital circuit(netlist and SDF) with ncverilog and analog circuit with SPECTRE (cadence AMS). what is the standard flow of SOC mix signal simulation? is this plan OK?
more, does any requirement for ASIC lib cell with virtuoso(import verilog)?
any more experience to share with me about such case?
THX.
i don't know much about mix signal simulation(only experience about digital ASIC).
a SOC design with digital logic circuit and analog IP. a plan to do a mix signal simulation.
digital circuit(netlist and SDF) with ncverilog and analog circuit with SPECTRE (cadence AMS). what is the standard flow of SOC mix signal simulation? is this plan OK?
more, does any requirement for ASIC lib cell with virtuoso(import verilog)?
any more experience to share with me about such case?
THX.