So I am desingning a SA ADC. The problem I am having is that how can I design the Successive Approximation Register (SAR). Do I design it using state diagrams?
If I use state diagrams (Moore State) to design it, then I will have to draw A LOT state diagrams for a SA ADC that can convert 8 bits. State diagrams is the only way that I know, is there any other way?
SA register can be made as a simple shift register which shifts a logic HIGH from MSB flop to LSB flop. Also it stores the current comparator input to the corresponding flop.
This should be very easy to implement.. either writing VHDL code or manual design...
There is no need for state machine if u know about how many cycles conversion takes place. u can generate the sample signal by delay elements(F/Fs) and use shift registers to transfer 1 from MSB F/F to other F/F for every conversion cycle. and latch the compartor output by generating the latch clock.
try "CMOS Analog to digital and Digital to Analog converters" by Rud van Plassche.....u get basic ideas...also u get information about good reference papers on SA ADCs
When I design ADC (any type) for algoritm or logic I use verilog code. And for SAR you mast have not only 1 reg. Your logic bloc must contain driver for S/H, driver for Comparator and DAC. Realize this functions in primitive logic components not use VERILOG is difficult.