subtraction two variables which has type time

[peaceful]

Hello,
I want to try compile execution time

at entity there is a line like that : output2 : out time

these are at architecture

signal output1 :time:=0 ns;
signal t0,t1 : time:=0 ns;
IF (the_end<='1') THEN
t1<=t0;
t0<=now;
output1<=(t0-t1);
--output2<=output1;

when I used like that.I'm getting output2 value 128. But output2 only used at entity.It has no assignment at architecture So I didn't understand the value.What is that? When I omit "--" operator at the --output2<=output1; output2 value doesn't have any value.

 

[joelby]

Is that really your complete code? Where is your "end if" statement? Is this a clocked or combinatorial process?

From what you've given. It looks like you'll form a transparent latch with the_end. Remember that every statement 'runs' simultaneously, so t1 will be assigned to t0, and t0 will be assigned to now, so all three will be equal to 'now'. HDL looks a bit like a normal (sequential) programming language, but it works in a completely different way.

I'm not sure why output2 would have a value of 128 when it's not assigned, but the value of an unassigned signal is pretty meaningless - I'm pretty sure that Xilinx ISim will give it an 'X' (undefined) value, but your simulation tool might differ (or are you synthesising this?)

 

[TrickyDicky]

you need to post your whole code:
Where is the declaration of the_end?

The code you posted using signals, not variables, hence why you are probably having problems (and if the_end is a std_logic, you code will never get executed anyway).

 

[peaceful]

the_end : OUT bit; when my calculation comes to end,the_end will be 1. end I want to get the time, when the_end is 1.Is it possible like that?

 

[joelby]

Yes, that's no problem,

I suggest you post the code in its entirety if you still need help.

 

[peaceful]

Yes, that's no problem,

I suggest you post the code in its entirety if you still need help.

I did it for an adder implemantation. And I want to get the how much clk it takes.And I add the code. But get errors like that.

 

[joelby]

How much clk does an adder take? What do you mean, exactly? And what sort of errors?

 

[peaceful]

yes exactly I want to know how much clk does an adder take.
How can do this.Not only for adder but also a divide operation. I want to know how much clk does these operations.
Or I explain like that
I implement same things at C. I get the run time with clock() functions.An its type at second
I want to compare VHDL imp. and C imp. at run time. So I must change clock time to other's.
clk to second, or second to clk.
I hope I can explain. This is hard to compare software run time and hardware run time, I know. But at somehow I must compare them.

 

[ads_ee]

yes exactly I want to know how much clk does an adder take.
How can do this.Not only for adder but also a divide operation. I want to know how much clk does these operations.
Or I explain like that
I implement same things at C. I get the run time with clock() functions.An its type at second
I want to compare VHDL imp. and C imp. at run time. So I must change clock time to other's.
clk to second, or second to clk.
I hope I can explain. This is hard to compare software run time and hardware run time, I know. But at somehow I must compare them.

Do you really mean to say:
yes exactly I want to know how many clocks cycles does the hardware implementation of the adder take.

This depends on the number of pipeline stages in the adder implementation. Sure you could put a counter in the design and sample the counter when it gets data and when the output is generated, but that's more work than looking at the RTL implementation of the adder.

You seem to be a SW type trying HDL...
HW runs in parallel and the concept of time as in seconds only exists if you count clock cycles using a physical counter and perform the conversion 1/Clock_Freq_in_Hz * delta_count_value.

If you're trying to make an embedded uP design with SW adder v.s. HW adder comparison then the counter makes sense, but you'll have to trigger the captures of counts from SW with a write or some custom instruction.

 

[joelby]

You could look at the maximum operating frequency of an adder or divider, but the clock speed will depend on:

- The implementation of the circuit, including its width and pipeline stages.
- The architecture you're targeting. A particular FPGA device? An ASIC?

Pipelining can allow you to trade maximum frequency against latency. You need to consider whether throughput or latency is most important to your application.

Even if you implemented a software adder or divider on your PC, there are a number of ways to do it - are your numbers floating point or integer? Can you use Streaming SIMD instructions? GPU acceleration? Do you care about the time just one operation takes, or do you care about how many operations you can efficiently do per second?

There are many variables here so you'll either need to be very specific about exactly what you want to benchmark, or do lots of benchmarks.