Can you please describe in more details "phase shifted channels" method?
It depends on the PLL's ability to create multiple phase shifted clocks. Most FPGA families also have dual-data-rate circuitry, that allows to sample on both edges of a clock.
One challenge is in combining the acquisition data from pahse shifted clock domains, the other in minimizing the data path/clock delay skew to achieve the intended accuracy.
You have to check the timing specification of your FPGA familiy.
Instead of shifting the sampling clock, you can also add logic cell delay to the datapath to create phase shifted channels. Buth the stability of clock cell delay can't compete with PLL phase taps, that are dividing the VCO period by an integer (e.g. 8) factor.