Structure in System Verilog

[Ahsan_Ali]

Hello Everyone. I want to ask that how a structure is synthesized in system verilog. Because Verilog and System Verilog eventually lead to some hardware. I just want to know what can be the best hardware representation for a structure. Example is:

struct str_sv{
        logic ip1;
        logic ip2;
        int z;
        bit b;
};

How the hardware of the above structure will look like?
You can help me by your own example code. Thanks!

Regards,
Ahsan

 

[glennramalho]

The structure is basically flatened by the tool. So, let's say yoyu create the struct:

typedef struct packed { .... } struct_t;

then you create the variables

struct_t a, b, c;

Internally the tool will flatten it and create the members individually. In Genus it uses an array like name. This is of coruse internal to the tool and you will see this in the final gatelevel netlist.

so you will have:
logic \a[ip1]
logic \a[ip2]
int \a[z]
bit \a
logic \b[ip1]
logic \b[ip2]
...
bit \c

Of course, the actual name might change from tool to tool. I think quartus instead calls them:
logic a.ip1
logic a.ip2
logic a.z
...


The tool will then use them normally with these as net names or register names. So you see the structure itself went away, the members of the struct are dealt with separately. And if one member is not used, synthesis will just wipe it away.

One hint though, I always use packed structs in synthesis. It just makes it easier to assign one to another. I guess it could work with unpacked structs, but I never tried it.