james09
Newbie level 4
Hi,all!
After testing,the following design failed.what is the right codes for structural style of 2-to-1 mux with selector input?
library ieee ;
use ieee.std_logic_1164.all;
entity mux2 is
port(a,b,s:in std_logic; o
ut std_logic);
end mux2;
architecture struct of mux2 is
component ha_en
port(a,s_bar:in std_logic;
c1ut std_logic);
end component;
component pa_en
port(b,s:in std_logic;
c2ut std_logic);
end component;
signal s2,o1,o2: std_logic;
begin
HA1:ha_en port map( s_bar => s2, a => a, c1 => o1);
HA2a_en port map(b => b,s => s,c2 => o2);
s2 <= not s;
o <= o1 or o2;
end struct;
After testing,the following design failed.what is the right codes for structural style of 2-to-1 mux with selector input?
library ieee ;
use ieee.std_logic_1164.all;
entity mux2 is
port(a,b,s:in std_logic; o
ut std_logic);end mux2;
architecture struct of mux2 is
component ha_en
port(a,s_bar:in std_logic;
c1
ut std_logic);end component;
component pa_en
port(b,s:in std_logic;
c2
ut std_logic);end component;
signal s2,o1,o2: std_logic;
begin
HA1:ha_en port map( s_bar => s2, a => a, c1 => o1);
HA2
a_en port map(b => b,s => s,c2 => o2);s2 <= not s;
o <= o1 or o2;
end struct;