Structral or Behavioral for begining

[pooyalock]

I have a computer design course which require learning Verilog.
It's optional to write our assignments structural or behavioral.
Which one do you think is more practical and better in such this matter?

 

[barry]

There is no "better". This is probably something constructed by college professors to give them something to teach. The reality is, both are used in the real world, and I don't think anybody actually thinks "Oh, I'm creating structural code now, then I'm going to create behavioral code".

This is like the "top down/bottom down" concept. Reality forces you to use both. I don't think ANYBODY (at least not me) has EVER done an entire design as Top Down or Bottom Up.

Just design it.

 

[pooyalock]

Where do you use each of them?

 

[TrickyDicky]

all designs are a mix of both. You have to isntantiate modules in almost any design.

A fully structural design would be tedius and require a huge amount of effort if you wanted to fill and FPGA. Thats why we write behavioural code. But for a simple design like a counter or an adder when you are learning, you would probably do best writing structural code to learn how to put logic together. When you understand this, you can move to more behavioural code.

 

[mrflibble]

I suspect this might be the starting point you are looking for: https://bit.ly/1liX520

 

[ads-ee]

A fully structural design would be tedius and require a huge amount of effort if you wanted to fill and FPGA. Thats why we write behavioural code. But for a simple design like a counter or an adder when you are learning, you would probably do best writing structural code to learn how to put logic together. When you understand this, you can move to more behavioural code.

I'm sure glad I graduated before HDLs existed. I would have wanted to quit school if they made me design a large circuit with structural Verilog. Personally I can't visualize a gate level netlist in Verilog or VHDL like I can with a schematic. I used to design FPGAs in schematics and I'll tell you it's tedious, but doing the equivalent gate level Verilog is worse.