strongarm comparator

[barbs2021]

Good day,

I am trying to simulate a strongARM comparator. As shown below, the inputs are indicated as Vin and Vref. In my testbench, I used vsource with a dc voltage of 1.8V for Vref and 1.8V sine wave (vsource) set at a frequency of 10 MHz for initial testing. Simulation is done using 180nm CMOS technology in SYNOPSYS Custom Designer Tool. Is this the right thing to do? I need corrections and suggestions. Hoping for kind and constructive response.

 

[sutapanaki]

What is your supply? What is your clock? Don't you think that showing some graphical information of your stimuli will go a long way?

 

[barbs2021]

What is your supply? What is your clock? Don't you think that showing some graphical information of your stimuli will go a long way?

My supply voltage is 1.8 V. I'm still not quite sure how the width and length of transistors should be designed so as to allow the comparator to operate at higher frequencies. Having said that, as for the moment I set the clock with 50 % duty cycle at 25 MHz.

 

[guntherleet]

Things you can consider checking are:
CM sensitivity - how input signal CM effect decision time/resolution
The effect of the frequency of the different phases(CLK)
The sizing of positive FB transistors and the parasitic capacitance on the output node should limit your comparator speed
Noise injection from CLK's switches could be very harmful.
Check the mismatch between comparator's branches, maybe apply some calibration method
the strongarm doesn't produce rail to rail output, maybe something to consider?

 

[sutapanaki]

My supply voltage is 1.8 V. I'm still not quite sure how the width and length of transistors should be designed so as to allow the comparator to operate at higher frequencies. Having said that, as for the moment I set the clock with 50 % duty cycle at 25 MHз

So, you are saying the supply is 1.8V and you are setting Vref=1.8V with a sine wave amplitude of 1.8V and you expect the comparator to toggle?