stray capacitance for a switched capacitor integrator

can somebody tell me why the
stray capacitance at the input and output of the switched capacitor circuit attached can be ignored?
I dont understand why it can be ignored if the output impedance is low.

It also says in the slide that if a stray capacitance is connected to a voltage source it can
again be ignored...Need some help understanding this...

In the ideal case a capacitance in parallel to a voltage source is charged immediately. In the context of that slide the charge deposited on the cap in parallel with Vin doesn't affect the rest of the circuit since the input voltage is still Vin no matter the cap.
The capacitor at the negative input of the opamp is connected to a virtual ground - that is both sides of the capacitor are connected to ground and hence that capacitor takes no charge.
The capacitor at the output of the opamp is driven by the opamp - that is, the opamp supplies the charge for it - something similar to the case when a voltage source is in parallel with a capacitor. This output capacitor, however, affects the dynamics of the circuit (opamp has some output resistance) and should be taken into account when investigating the loop stability.

thank you. I understand now.

It should be noted that capacitance at the negative input virtual ground also affects the circuit dynamics since it increases the settling time of the op amp.

Yes, that is correct. It affects the feedback factor of the amplifier.