zhangljz
Member level 5
Hi,
I am using encounter for PR, and I tried a very simple design but found unconstrained path. the netlist for PR is :
![pr_1.jpg pr_1.jpg](https://www.edaboard.com/data/attachments/60/60883-0f2645c91377ab0146c8a34302795a30.jpg)
Only one flip-flop
the constrain file is
![pr_2.jpg pr_2.jpg](https://www.edaboard.com/data/attachments/60/60884-e95c1ee5589157c60fbb0896062ecedc.jpg)
after I import the design, when I check" report_timing -unconstrained "
I got 3 unconstrained points, including the clk, and rstb. even the path between clk port and flip-flop clock pin are unconstrained. I am confused.
![pr_3.jpg pr_3.jpg](https://www.edaboard.com/data/attachments/60/60885-15f540f03511ae5192900a8afc731644.jpg)
Anybody knows how to fix this ?
Thank you
I am using encounter for PR, and I tried a very simple design but found unconstrained path. the netlist for PR is :
![pr_1.jpg pr_1.jpg](https://www.edaboard.com/data/attachments/60/60883-0f2645c91377ab0146c8a34302795a30.jpg)
Only one flip-flop
the constrain file is
![pr_2.jpg pr_2.jpg](https://www.edaboard.com/data/attachments/60/60884-e95c1ee5589157c60fbb0896062ecedc.jpg)
after I import the design, when I check" report_timing -unconstrained "
I got 3 unconstrained points, including the clk, and rstb. even the path between clk port and flip-flop clock pin are unconstrained. I am confused.
![pr_3.jpg pr_3.jpg](https://www.edaboard.com/data/attachments/60/60885-15f540f03511ae5192900a8afc731644.jpg)
Anybody knows how to fix this ?
Thank you