I guess it turns on the PNP when the capacitor gets to 10V, which turns on the NPN which keeps the PNP on until the capacitor reaches 0V.
Basically.
That transistor combination acts rather like an SCR.
When the capacitor voltage rises high enough to turn on as determined by the base voltage from divider resistors R4 and R5, T2 turns on, which turns on T1, discharging the capacitor.
When the capacitor voltage drops to the base-emitter voltage of T2, where T1 and T2 turn off, the cycle restarts.
Below is the LTspice sim of a similar, slightly more complex circuit:
Here the Q3 bootstrap generates a constant voltage across R4, and thus a constant-current to C1 for a linear sawtooth.
Q4 is an emitter-follower to buffer the capacitor sawtooth output.
D1 is to prevent reverse over-voltage of Q1's base-emitter junction
Note the short time that transistors Q1 and Q2 are on to discharge the capacitor (yellow traces).
The constant current of approximately 0.6V / R4 charges the capacitor up to approximately 0.6V above the divider voltage from R2 and R3, when discharge occurs, so using the capacitor equation for voltage versus charge current, you can calculate the sawtooth period.