Storing data from a small bank of DFFs continuously to a larger bank

[souryadey92]

Hello,

I have a bank of 16 D-FlipFlops where data keeps getting latched on every clock cycle. But the number of new data values is not fixed. In the first cycle, say 5 new values come in. These are stored in DFFs 1-5. For the 2nd cycle, 3 new values come in. Since a counter keeps track of the last new address, these 3 values get latched to DFFs 6-8. This continues and when 16 is reached, the data wraps around back to DFF 1. So if 14 new values come in the 3rd cycle, they get latched to DFFs 9-16 and then 1-6, overwriting previous values. The important thing to note is that a maximum of 16 new values can come in a single cycle, that's why I have a bank of 16 DFFs. Call this Bank 1.

I have another bank of a lot of DFFs (say 1000). Call this Bank 2. I want to latch only the new values which come into Bank 1 to Bank 2 on every cycle. Also, I want Bank 2 to store the values sequentially, i.e. 1-5 get latched from Bank 1 to DFFs 1-5 of Bank 2 after the 1st cycle, then DFFs 6-8 of Bank 2 on the 2nd cycle, then DFFs 9-22 of Bank 2 on the 3rd cycle, and so on.

So here's my question: What sort of connections do I make to achieve this? Bank 1 has 16 outputs, so what kind of block can I design in between Banks 1 and 2 to achieve this functionality? I have thought of 2 things so far:
1) Store starting and ending addresses of Bank 1 on every cycle. That way the newly latched values can be pinpointed. But how do I ensure these values go into the proper locations of Bank 2?
2) Use a 16x1 MUX at the input of each DFF in Bank 2, which tells each DFF where to get data from. But this requires a LOT of hardware. I am wondering if there's a better way.

Any help would be appreciated. Regards,
Sourya

 

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I believe the reason there haven't been any replies yet is due to the fact there are missing(vague) requirements.

Are the transfers into the 16 DFFs (1-16 at a time) done in a single clock cycle?
Are the transfers from the 16 DFFs (whatever the number that was loaded previously) done in a single clock cycle to the 1000+ DFFs bank?

If both the above are yes then 16-to-1 multiplexers and lots of control logic for the selects to do the transfer. The only way to make it more efficient is to trade broadside parallel logic for time multiplexed logic, but there are no specifications in your description that would indicate that could be done.

 

[souryadey92]

Thanks for replying. Both answers to your questions are yes.

I have already considered using 16x1 MUXes and control logic to decide which ones are the new samples. I was looking for an alternate way. I am confused as to what you mean by trading broadside parallel logic for time multiplexed logic. If you could elaborate, I could give more specifications to determine its feasibility.

Thanks.

 

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What you are currently looking at is doing it in parallel 1000's of 16x1 muxes to select the input DFF to load the larger 2nd buffers.

The only other option I can see is if you can afford to clock the up to 16 DFFs out and load them one at a time into the 2nd bank of DFFs (i.e. time multiplex the 16x1 mux and just select the correct load signal. I suspect this isn't feasible, but as I don't know the exact specification of the incoming data you would have to determine if that is really true or not.

 

[D.A.(Tony)Stewart]

A CPLD chip can do all of this with a bi-directional bus to reduce pin count. A good design starts with a State Diagram.