Stopping a clock while synchronous reset

[ivlsi]

Hi All,

There is a technique to stop clocks during synchronous reset. The question is "Why?"

Synchronous resets are synchronous to clocks, so they should occur with the safe timing (without removal or recovery violations). So, why stopping the clocks?

One of the answers, which I got, is

Thank you!

 

[D.A.(Tony)Stewart]

If synchronous resets occur at same edge as clock, a race condition or glitch may be produced and if that matters, reset should be skewed on on alternate phase of clock unless this metastable condition can be avoided or doesn't matter.