xtcx's proposal is the only thing that would work for an "std_logic_vector".
TrickyDicky's suggestion will convert a "signed" or "unsigned" vector to an integer - As he mentioned, it is however the formal and standard conversion to use.
std_logic_vector uses the non-standard synopsis liabraries.
TrickyDicky's example does convert std_logic_vector to integer. The conversion is done in two steps because you must specify if there is a sign bit or not in the std_logic_vector.
conv_integer is not part of the official standard libraries, and it is confusing because you can't mix signed and unsigned in one entity.
It is defined for std_logic_vector in the non-standard libraries std_logic_unsigned and std_logic_signed, but you can only use one of them in an entity.
It seems to be very hard for people to switch to numeric_std from the old non-standard libraries std_logic_arith, std_logic_unsigned and std_logic_signed.
It requires a slightly different coding style, and I therefore strongly recommend beginners to only use numeric_std.
The standard library numeric_std has been available for about 20 years, so I can't believe that some VHDL books that you buy today use the old non-standard libraries.
If you see a book or tutorial that use the old libraries, burn it and get something else!
Otherwise you will get bad habits that can be difficult to break (like smoking).