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std_logic_vector to integer

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dksagra

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how to convert std_logic_vector to integer...
in the problem, i have std_logic_vector of 16 bit and signed..

please help me out..

regards
 

use ieee.numeric_std.all;

my_integer <= to_integer( signed(my_slv) );
 
I think we can also use
my_integer <= conv_integer(std_logic_type);
 

xtcx's proposal is the only thing that would work for an "std_logic_vector".
TrickyDicky's suggestion will convert a "signed" or "unsigned" vector to an integer - As he mentioned, it is however the formal and standard conversion to use.

std_logic_vector uses the non-standard synopsis liabraries.
 

xtcx's proposal is the only thing that would work for an "std_logic_vector".
TrickyDicky's suggestion will convert a "signed" or "unsigned" vector to an integer - As he mentioned, it is however the formal and standard conversion to use.

std_logic_vector uses the non-standard synopsis liabraries.
TrickyDicky's example does convert std_logic_vector to integer. The conversion is done in two steps because you must specify if there is a sign bit or not in the std_logic_vector.

conv_integer is not part of the official standard libraries, and it is confusing because you can't mix signed and unsigned in one entity.
It is defined for std_logic_vector in the non-standard libraries std_logic_unsigned and std_logic_signed, but you can only use one of them in an entity.

It seems to be very hard for people to switch to numeric_std from the old non-standard libraries std_logic_arith, std_logic_unsigned and std_logic_signed.
It requires a slightly different coding style, and I therefore strongly recommend beginners to only use numeric_std.
The standard library numeric_std has been available for about 20 years, so I can't believe that some VHDL books that you buy today use the old non-standard libraries.
If you see a book or tutorial that use the old libraries, burn it and get something else!
Otherwise you will get bad habits that can be difficult to break (like smoking).
 

It requires a slightly different coding style, and I therefore strongly recommend beginners to only use numeric_std.

What do you mean by "different coding style"?
 

What do you mean by "different coding style"?

The main thing is to use types "unsigned" and "signed" instead of "std_logic_vector" for signals and ports when you want to use them for arithmetic operations.
With the old libraries, std_logic_vector is often used for "everything". If you do it like that with numeric_std the code will be full of conversions and castings.
 

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