dumindu89
Member level 1
Hello I am trying to convert a std_logic_vector to integer. Here is how I did the std_logic_vector to integer conversion.
But this didn't gave the correct output when I enter 4 as binary (0000000100) in the simulation via Quartus II 7.2 (The device is : MAX II EPM240T100C5). I mean the divider should divide the clk by 4.
Instead of that I observed around divide by 5 or 6.
Please help me to solve this case.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity programmable_divider is
port( clk : in std_logic;
clk_out : out std_logic;
divide_value : in std_logic_vector (9 downto 0)
);
end programmable_divider;
architecture Behavioral of programmable_divider is
signal counter,programmable_divide: integer := 0;
begin
programmable_divide <= to_integer(unsigned(divide_value(9 downto 0)));
But this didn't gave the correct output when I enter 4 as binary (0000000100) in the simulation via Quartus II 7.2 (The device is : MAX II EPM240T100C5). I mean the divider should divide the clk by 4.
Instead of that I observed around divide by 5 or 6.
Please help me to solve this case.