"std_logic_vector" Related Questions

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dzafar

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I have three question!

Q1. Say:

signal X, Y: std_logic_vector (7 downto 0);
variable change_bit: std_logic;

change_bit = '0';

X <= "11100110";
Y <= X;

Y(6) <= change_bit; -- Is this valid? i.e. does Y now equal "10100110"?

Q2. Can we initialize an array using pre-defined attributes?

Say:

signal X: std_logic_vector (7 downto 0);
signal Y: X' range; -- is this valid? i.e. does this initialize Y to be (7 downto 0)?

Q3. What happens when:

signal X: std_logic_vector (7 downto 0);
signal X: std_logic_vector (3 downto 0);?
 

Q1. Say:

signal X, Y: std_logic_vector (7 downto 0);
variable change_bit: std_logic;

change_bit = '0';

X <= "11100110";
Y <= X;

Y(6) <= change_bit; -- Is this valid? i.e. does Y now equal "10100110"?
Click to expand...
Variables can only exist in a process, so I will assume it was defined in a process.
Wrong assignment to the variable, it should be like this:
change_bit := '0';
Answer Q1: Yes it is valid.

Q2. Can we initialize an array using pre-defined attributes?

signal X: std_logic_vector (7 downto 0);
signal Y: X' range; -- is this valid? i.e. does this initialize Y to be (7 downto 0)? <<<<---------- WRONG
Click to expand...
Where I have wrote WRONG, it should be like this:
signal Y: std_logic_vector(X'range); <<<---- THIS IS VALID

Q3. What happens when:

signal X: std_logic_vector (7 downto 0);
signal X: std_logic_vector (3 downto 0);?
Click to expand...
ERROR, signal "X" has 2 definitions.
 

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