[SOLVED] STD CELL pin minimum area violation fix

[Vahe Yeghiazaryan]

HI ALL,

Does anybody know which commands/options to use to force SOC Encounter to fix standard cell's pin minimum area violations whicle routing, if initially it wasn't saticfied in cell itself.

Thanks in advance.

Vahe

 

[artmalik]

This is not a recommended flow because this will increase the run time....
a) The standard cells should take care of this automatically at the design stage
b) The vias can be constructed through the tech file in such a way that it drops vias with minimum area rule compliance.
the first option is preferable.

 

[Vahe Yeghiazaryan]

HI artmalik,

thanks a lot for for reply.

Do I understand correctly point "b", should have vias metal shapes with minimum area?

Thanks

 

[artmalik]

The tech file has definition for the various vias that can dropped. the via will be defined as width, area, shape and enclosure in each metal layer. So when the vias are dropped on the pin, it will automatically create a metal shape which will take care of the minimum required DRC rules. Usually the basic tech file is provided by the vendor. People write special rules for important pins like clock pins should have two vias for example.