Hi,
What is the code context? Is it intended to be in a combinational block, or
in a sequential block?
It should be ok if you put reg_a <= ~reg_a in a sequential block, with
posedge or negedge of clock as your sensitivity list events. But you cannot
do something like the following:
@ (a or b)
begin
reg_a <= ~ reg_a
end
By the way, if you want to produce a clock signal in an FSM, better to generate
a control signal to a gated clock, and generate the clock seperately..