Statement unreachable (Branch condition impossible to meet)

[iamczx]

branch condition impossible to meet)

When I read_verilog , this warning come out. And a strange things happend when I check my code:
there is a case sentence in the code:
case(current_state):
`IDLE:
.....
......
`READ:
begin
wr<= ~wr; //here is the probem
........
end
.......
endcase

if i comment the wr <= ~ wr; or change it to: wr <= constant;(such as 1'b1);
the warning will disappear!

but ,why ?? The `READ branch is arrivable in fact, and why it becomes unreachable when the sentence " wr <= ~wr;" exist.
Anyone can tell me why? Thanks in advance.

 

[nand_gates]

unreachable branch verilog

Not clear exactly what u r doing?
Are you trying to synthesize ur code using synopsys DC?
Can u post the complete code here at least the module having error?
The case statement is for combo logic or registers??

 

[jas_bakshi]

branch condition impossible to meet

Hi

This condition may occur when u are trying to jump from one state to other but simultaneously two next states are getting generated.Say checking same conditions for two next states.So u should check the state transition logic in your code.

Regards

Jas

 

[iamczx]

unreachable branches

Not clear exactly what u r doing?
Are you trying to synthesize ur code using synopsys DC?
Can u post the complete code here at least the module having error?
The case statement is for combo logic or registers??

the code is too much..
and I made some errors in my orin post.

it should be wr <= ~wr; i want to produce a write clock .

Added after 4 minutes:

Hi

This condition may occur when u are trying to jump from one state to other but simultaneously two next states are getting generated.Say checking same conditions for two next states.So u should check the state transition logic in your code.

Regards

Jas

hello jas_bakshi, I had excluded this possibility . The most strange thing is that this warning will disappear at once if only I comment the sentence "wr <= ~wr;" or assign wr <= constant;

 

[penrico]

branch condition impossible

It's hardware design, so, the "wr" signal is finally a wire, so you can't assign a signal like "~wr" to same wire that is "wr". Only way is making "wr" signal be flip-flops, I don't know if it's inside other condition that produces a flip flop or a wire, if it's a wire you can't do it.

 

[iamczx]

error(30,20): statement not reachable

It's hardware design, so, the "wr" signal is finally a wire, so you can't assign a signal like "~wr" to same wire that is "wr". Only way is making "wr" signal be flip-flops, I don't know if it's inside other condition that produces a flip flop or a wire, if it's a wire you can't do it.

hi penrico, I define the wr as reg, and I think the "wr <= ~wr " should be inferred as a register ,which output is feed to the register's input through an inverter.

 

[rprince006]

statement branch condition

Hi,

What is the code context? Is it intended to be in a combinational block, or
in a sequential block?

It should be ok if you put reg_a <= ~reg_a in a sequential block, with
posedge or negedge of clock as your sensitivity list events. But you cannot
do something like the following:

@ (a or b)
begin
reg_a <= ~ reg_a
end

By the way, if you want to produce a clock signal in an FSM, better to generate
a control signal to a gated clock, and generate the clock seperately..

 

[iamczx]

statement unreachable

Hi,

What is the code context? Is it intended to be in a combinational block, or
in a sequential block?

It should be ok if you put reg_a <= ~reg_a in a sequential block, with
posedge or negedge of clock as your sensitivity list events. But you cannot
do something like the following:

@ (a or b)
begin
reg_a <= ~ reg_a
end

By the way, if you want to produce a clock signal in an FSM, better to generate
a control signal to a gated clock, and generate the clock seperately..

hi,rprince006, it's a sequential block. the attach is my code.
if use gated clock ,the new output clock pulse width is equal to the input clock,isn't it?
I need a double pulse width clock.

 

[nand_gates]

how do you say unreachable in french?

hi,
Why dont you post ur complete statemachine code here??
I think what you have posted is just a output decoder part of ur statemachine.

 

[haosg]

how do you say unreachable in french

it is only a combinational loop, so it is only warning.
so I don't know why the "unreachable branch " occured,

 

[iamczx]

error(35,9): statement not reachable

it is only a combinational loop, so it is only warning.
so I don't know why the "unreachable branch " occured,

always @(posedge clk)
....

why you say it a combinational loop?

 

[power-twq]

Re: Statement unreachable (Branch condition impossible to me

please check your always nlock is sequential or combinational?

if your always block is sequential, This writing is no problem.

if your always block is combinational , that's big problem,

you can't write wr<= ~wr;

When I read_verilog , this warning come out. And a strange things happend when I check my code:
there is a case sentence in the code:
case(current_state):
`IDLE:
.....
......
`READ:
begin
wr<= ~wr; //here is the probem
........
end
.......
endcase

if i comment the wr <= ~ wr; or change it to: wr <= constant;(such as 1'b1);
the warning will disappear!

but ,why ?? The `READ branch is arrivable in fact, and why it becomes unreachable when the sentence " wr <= ~wr;" exist.
Anyone can tell me why? Thanks in advance.

 

[iamczx]

hi power-twq, It's sequential block.
I still don't know why the dc report this waring

 

[BrownBear]

Re: Statement unreachable (Branch condition impossible to me

The fact that wr is declared as reg doesn’t mean that wr is FF. In your verilog code
the behaviour of wr is net (wire). So the code wr <= ~wr generates combinational loop, which is unacceptable in poor digital design.

 

[iamczx]

hi BrownBear,I know this point.
And in my code,the wr act as reg in fact. The code I
have post in the 8th article in this topic.
Thanks