state machine problem in VHDL..

[Iouri]

cnt >4096 hwo that would be possible?

 

[leoren_tm]

uhm.....try chaging it..and run it..
i think it willnot work

 

[wice]

hi leoren_tm
i think the clock devide part should be writen in this way:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY main IS
PORT(
input_old : in std_logic_vector( 1 downto 0);
clk, pb : in std_logic;
output : OUT STD_LOGIC_VECTOR(10 downto 0));
END main;

ARCHITECTURE struct OF main IS
TYPE STATE_TYPE IS (s0, s1, s2, s3);
signal state: STATE_TYPE;
signal clk_delayd : std_logic ;
signal input_new : std_logic_vector(1 downto 0);
signal cnt : std_logic_vector(11 downto 0);
BEGIN

PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
cnt <= cnt + 1;
IF (cnt = 2048) THEN
clk_delayd <= '1' ;
ELSIF (cnt =0) THEN
clk_delayd <= '0';
else
null;
END IF;
END IF;
END PROCESS;
in this way you can get the aera decreased and timing slack increased.

Added after 7 minutes:

a even beter way :
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY main IS
PORT(
input_old : in std_logic_vector( 1 downto 0);
clk, pb : in std_logic;
output : OUT STD_LOGIC_VECTOR(10 downto 0));
END main;

ARCHITECTURE struct OF main IS
TYPE STATE_TYPE IS (s0, s1, s2, s3);
signal state: STATE_TYPE;
signal clk_delayd : std_logic ;
signal input_new : std_logic_vector(1 downto 0);
signal cnt : std_logic_vector(11 downto 0);
BEGIN

PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
cnt <= cnt + 1;
END IF;
end process;
clk_delayd <= cnt(11);

END PROCESS;

 

[leoren_tm]

null;???

uhmm
how it wotks??
im doing now a trafic ligth ..
pls help me..
thx