state machine error - case statement warning

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tyj0423

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state machine errors

i designed a state machine,when proeceeing the design ,the RTL of state machine is correct.
BUT,when i generate its symbol,and conenct it in the top entity,the RTL state machine is not same as the sub_module, and generate the warning
Warning (10272): Verilog HDL Case Statement warning at controlflat.v(112): case item expression covers a value already covered by a previous case item

why?
how should i do
 

state machine error

check all your case statements... you might have repeated one of the cases, at least according to the rror report.
 

state machine error

Have you coded the FSM correctly? Are the states unique or one hot encoded?
 

Re: state machine error

All state need to be unique (not sure I understand the question). How you encode the state does not matter as the sythesis tool will re-incoded them to as is sees fit anyway.

Try to use names to encode your state (easier to read - I don't know how to do this with Verilog).
 

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