state machine coding styles

[hover]

Hi, below there are two types of state machine coding styles.

1. always@(posedge clk or negedge rst_n)
    ...
       current_state <= next_state;
    ...
    always@(current_state)
    ...
    case(current_state)
    ...
       s1:
            if...
              next_state = s2;
            ...
    ...
    always@(posedge clk or negedge rst_n)
    ...
      else
         a <= 1'b0;
         b <= 1'b0;
         c <= 1'b0;
         case(current_state)
            s1:
                  a<=1'b1;
            s2:
                  b<=1'b1;
            s3:
                  c<=1'b1;
            default:
        ....

2. always@(posedge clk or negedge rst_n)
    ...
       current_state <= next_state;
    ...
    
    always@(current_state)
     ...
     a = 1'b0;
     b = 1'b0;
     c = 1'b0;
     case(current_state)
     ...
       s1:
            if...
              begin
                  next_state = s2;
                  a=1'b1;
              end
       s2:
            if...
              begin
                  next_state = s3
                  b=1'b1;
              end
        s3:
            c=1'b1;
        default:
        .........

It is said that the first one format of the two state machines is a standard and better one. But for the first one, there is one clock period latency with a, b and c signal. For some cases, it will not be good.

 

[spauls]

Io latency will not be affected much by State machine logic.

 

[r63511]

in the second design, the output might contain a lot of glitches, which is very dangerous if used directly to drive other combinational logic.