hover
Junior Member level 2
Hi, below there are two types of state machine coding styles.
It is said that the first one format of the two state machines is a standard and better one. But for the first one, there is one clock period latency with a, b and c signal. For some cases, it will not be good.
Code:
1. always@(posedge clk or negedge rst_n)
...
current_state <= next_state;
...
always@(current_state)
...
case(current_state)
...
s1:
if...
next_state = s2;
...
...
always@(posedge clk or negedge rst_n)
...
else
a <= 1'b0;
b <= 1'b0;
c <= 1'b0;
case(current_state)
s1:
a<=1'b1;
s2:
b<=1'b1;
s3:
c<=1'b1;
default:
....
2. always@(posedge clk or negedge rst_n)
...
current_state <= next_state;
...
always@(current_state)
...
a = 1'b0;
b = 1'b0;
c = 1'b0;
case(current_state)
...
s1:
if...
begin
next_state = s2;
a=1'b1;
end
s2:
if...
begin
next_state = s3
b=1'b1;
end
s3:
c=1'b1;
default:
.........
It is said that the first one format of the two state machines is a standard and better one. But for the first one, there is one clock period latency with a, b and c signal. For some cases, it will not be good.