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start up circuit problem

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devop

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hi ,can anyone tell me how the start up circuit works?
 

mpig09

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Dear devop :

When VDD increases from 0V-->VDD slowly and under 1V, inverter(P2, N2)
input is "Logic 1", then P3 turn on.

When VDD increases over 1V, inverter(P2, N2) input is "Logic 0" then P3 turn
off.


I hope this will help you.
mpig
 

vicky

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HI DEAR,

kindly clear one thing please that are both sources are vdd or one of these is vss source, kindly clearify
 

devop

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mpig09 said:
Dear devop :

When VDD increases from 0V-->VDD slowly and under 1V, inverter(P2, N2)
input is "Logic 1", then P3 turn on.

When VDD increases over 1V, inverter(P2, N2) input is "Logic 0" then P3 turn
off.


I hope this will help you.
mpig
can you explain why inverter(P2, N2) input is "Logic 1", ???

vicky: I don't undestand you.
picengineer:I get the circuit from a real chip,but I don't know how the circuit work,maybe it's useless,who konws :)
 

mpig09

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Dear all :

It is my mistake, I think vicky's suggest is right.
When the gate of P1 connects vss, the function looks right.

The "logic 1" is not real power supply voltage, when vdd increase
but under 1V, P1 will output the VDD value, the value is under 1V, but this
voltage need to driver N2 to turn on, so the size of NMOS I think can't the
same when you want a start up function.


mpig
 

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