Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

start up circuit problem

Status
Not open for further replies.

devop

Full Member level 1
Full Member level 1
Joined
Dec 5, 2006
Messages
99
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,973
hi ,can anyone tell me how the start up circuit works?
 

mpig09

Full Member level 4
Full Member level 4
Joined
Aug 26, 2005
Messages
231
Helped
8
Reputation
16
Reaction score
2
Trophy points
1,298
Location
Taipei
Activity points
2,803
Dear devop :

When VDD increases from 0V-->VDD slowly and under 1V, inverter(P2, N2)
input is "Logic 1", then P3 turn on.

When VDD increases over 1V, inverter(P2, N2) input is "Logic 0" then P3 turn
off.


I hope this will help you.
mpig
 

vicky

Full Member level 4
Full Member level 4
Joined
Aug 11, 2004
Messages
235
Helped
23
Reputation
46
Reaction score
4
Trophy points
1,298
Activity points
2,404
HI DEAR,

kindly clear one thing please that are both sources are vdd or one of these is vss source, kindly clearify
 

devop

Full Member level 1
Full Member level 1
Joined
Dec 5, 2006
Messages
99
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,973
mpig09 said:
Dear devop :

When VDD increases from 0V-->VDD slowly and under 1V, inverter(P2, N2)
input is "Logic 1", then P3 turn on.

When VDD increases over 1V, inverter(P2, N2) input is "Logic 0" then P3 turn
off.


I hope this will help you.
mpig
can you explain why inverter(P2, N2) input is "Logic 1", ???

vicky: I don't undestand you.
picengineer:I get the circuit from a real chip,but I don't know how the circuit work,maybe it's useless,who konws :)
 

mpig09

Full Member level 4
Full Member level 4
Joined
Aug 26, 2005
Messages
231
Helped
8
Reputation
16
Reaction score
2
Trophy points
1,298
Location
Taipei
Activity points
2,803
Dear all :

It is my mistake, I think vicky's suggest is right.
When the gate of P1 connects vss, the function looks right.

The "logic 1" is not real power supply voltage, when vdd increase
but under 1V, P1 will output the VDD value, the value is under 1V, but this
voltage need to driver N2 to turn on, so the size of NMOS I think can't the
same when you want a start up function.


mpig
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top