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Standby Mode , Sleep Mode and Power Saving Mode Operation

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Dec 10, 2004
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Are these 3 operation mode give a similar meaning and functionality in ASIC design?

In my opinion, it looks like these three operations are the same in functionality; to save power. Thus, I need a gated clock in my design. Is it correct?

Please enlighten me.
All comments and/or suggestions are welcomed.


Re: Standby Mode , Sleep Mode and Power Saving Mode Operatio

Well in any ASIC there are three or 4 states of the chip depending on APplication.

1.The chip is completely Powered down(This could be achieved with disabling the Regulator enable of the onchip regulator)COmplete power down 0mA current

2.The external source of the clock is gated on chip, again almost power down as there is only leakage current.

3.Partial gating of the clock based on the particular parts of the chip.
4.Aprt from this you can have some modules on the chip which have their enables and operate only when enabled.


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Re: Standby Mode , Sleep Mode and Power Saving Mode Operatio

Hi kgeorge123,

From your replied, I would said 1, 2 and 3 is Power Save mode operation. This is because either we disable the regulator on chip or stop the clock.

As for no. 4, it looks like when we have an Enable pin on module. We can put certain module on standby mode or sleep mode.

My conclusion is these 3 modes may vary a lot depending on how the product is defined. For some design, a standby mode is when the whole chip goes in standby whereby most part are down but some critical logic is still up in standby. Power save mode is in operation mode but some not used clocks are switched off.
Finally, it really depends on the datasheet on how these 3 modes are defined.


Re: Standby Mode , Sleep Mode and Power Saving Mode Operatio

no_mad said:
Finally, it really depends on the datasheet on how these 3 modes are defined.

For Standby Mode, maybe clock is gating off, maybe clock is running and function is disable.
For Sleelp Mode, there are normal sleep mode and deep sleep mode.
For Power Saving Mode, maybe turn off some clocks. Mostly, reduce the frequency of clock ratio.

Select the suitable mode for your requirements.

In order to design efficient power saving logic, a lot of gated clocks are needed. And with several levels. It's like a tree from root to all branches with a lot of valves whose on/off state can be controlled by register or state machine.

Netlist Debug/ECO in GUI mode

Will gating clock cause problem during synthesis?

No big problems. Only that sometime, timing is hard to meet. And there is more hold time violations than normal design if logic boundary between gated-clocks are not taken care of properly.

Netlist Debug/ECO in GUI mode

Re: Standby Mode , Sleep Mode and Power Saving Mode Operatio

The three main sources of power consumption are inrush, standby and dynamic. Current associated with the power-up sequence of a device is referred to as inrush current. Standby power, also known as static power, is the power of a device when the power lines are active and when there is no switching activity on the I/Os. Dynamic power, also referred to as switching power, is the power associated with a device during normal operation.

Inrush current is device-specific. For example, SRAM-based FPGAs have a high inrush current because on power-up these devices are not configured and need to actively download data from external memory chips to configure their programmable resources, such as routing connections and lookup tables. Conversely, anti-fuse-based FPGAs do not have a high inrush current since they do not require power-on configuration.

Much like inrush power, standby power depends heavily on the electrical characteristics of a component. Due to the extensive number of SRAM cells within SRAM FPGA interconnects, they can consume hundreds of milliamps even at standby. Since anti-fuse FPGAs have metal-to-metal interconnects, they do not require the additional transistors, and hence power, to retain interconnects. However, for both FPGA process types, leakage current increases as process geometry shrinks, which exacerbates the power problem.

As an additional dilemma, dynamic power can easily be several times greater than standby power. Dynamic power is proportional to the frequency of charging and discharging of internal parasitic capacitances of a component, such as registers and combinatorial logic, so optimizations are generally design-oriented.

Cutting power consumption
The following are some techniques that can be used to minimize power consumption within an FPGA design:

State machine encoding. A number of logic resources are defined by the type of finite state machines implemented. One-hot state machine encoding creates state machines with one flip-flop per state and decreased combinatorial logic width compared with Gray and binary state machines. The lower utilization of one-hot state machines vs. Gray and binary state machines results in a more power-efficient design. Some synthesizer software automatically encodes state machines, but the most effective way is to define state values directly in the HDL code.
Guarded evaluation. The key to guarded evaluation is to stop inputs from propagating down to additional logic blocks if the resulting outputs do not require updating. Guarding the evaluation of input signals ensures that outputs change values only when it is appropriate. As a result, unnecessary output switching is minimized.
Adding latches at the inputs of large combinatorial logic (e.g., wide bus multiplexer) can suppress invalid switching activity, because inputs are latched only when the outputs are supposed to be updated. Similarly, control registers can be implemented to enable or disable lower-level modules (e.g., state machines in submodules). Holding large buses and submodules in a constant state helps reduce the amount of irrelevant switching.

Combinatorial loops. Occasionally, it is possible for a designer to inadvertently create combinatorial loops in an FPGA design. These loops are formed when there is a group of related combinatorial logic that, under certain conditions, will oscillate indefinitely. Oscillators draw excessive amounts of current in FPGAs. Therefore, it is a good idea to evaluate out oscillators or make sure that any feedback logic is gated by a register prior to reevaluation.
Gated clocks. Temporarily unused modules can have their clocks slowed or stopped. Power savings comes from clocks only being provided to certain portions of the design at any given time. Gating a clock contributes to a significant amount of power savings because the number of active clock buffers reduces the number of toggling flip-flops decreases, and consequently the fan-out of those flip-flops will be less likely to toggle. Gating clocks requires careful planning and partitioning of algorithms, but the power savings can be considerable.
System-level savings
Power savings can also be realized at the system level in the following areas:

System clock speeds. System clock frequency has a dramatic impact on the overall power consumption of a board, since clock signals have the highest switching activity and capacitive load. Clock speed directly relates to bandwidth performance, however. To achieve an optimum balance between power and throughput, a slower clock can be supplied to components that do not require a fast clock. For devices that are critical to bandwidth, provide a fast clock, or use a built-in phase-locked loop (when available) to internally generate a fast clock for the specific modules that require faster performance.
Component enabling. Sometimes output values are evaluated even though their behavior is not necessary for the current function. To alleviate the superfluous power consumption caused by unused I/O, a system controller can be mapped to the FPGA to power down or disable devices that are temporarily unused. A system controller can deactivate the enable signal to a device when that device is irrelevant to the current operation, or put a device in its sleep mode when that device will not be accessed for an extended period of time. Implementing such a system controller in a low-power FPGA reduces the overall switching activity of the system, and intelligently keeps the appropriate devices in their sleep modes. Component enabling is similar to guarded evaluation except that component enabling is implemented at the system level to control components on the board instead of modules in an FPGA.
Intelligent coprocessor. Liquid-crystal display screens and microprocessors typically take up most of the power budget in a design so it is general practice to dim or partially disable LCD screens to save power. Likewise, keeping a microprocessor in its sleep mode also lengthens battery life.
Unfortunately, microprocessors usually need to handle interrupt service routines across multiple devices, which tends to keep the microprocessor out of sleep mode. For that reason, offloading peripheral operations and interrupt control to a low-power FPGA significantly reduces power consumption. A low-power interrupt controller or data coprocessor implemented in an FPGA can handle some of the interrupt activity on its own, and avoid having to wake up the microprocessor for lower-priority transactions.

For systems where low power is vital, employing power reduction design techniques with appropriate low-power programmable logic devices helps keep system power consumption to a minimum.

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