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standby leackage power reduction using Dual vth

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Dec 27, 2005
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standby leackage power reduction using Dual vth
iam doing project in this ,iam facing problem to start.iam devoloping in c.please any one help me.

I didnt understand whats your problem. As you said Multi-Vt synthesis is used for reducing leakage power. The timing critical paths in the design will be using Low-Vt cells for high speed. And Non Critical paths use High Vt cells. High Vt cells has less leakage power , but Propagation delay is more compared to low-Vt cells.

to reduce dynamic leakage power, we can use muti voltage cells.

I have just involved in a project , that when standby cutting the power supply for the most modules and only resever power for system control partion. This will decrease the leakage power. But we have to insert isolation cell to hold some control signals (output from the cutting power supply cell to resever power modules).

i want code for "Standby Leakage Power Reduction using Dual Vth in Domino ckts".u have code ,send me

what type of code?? a dc script for multi-vth synthesis??

i want code in c.can any one post it???

Does DC support this method?How it know which cell used during synthesis if these cells exist in library?

POwwer compiler supports multi vth synthesis

Benchmark ckt's taking as input files ,pls help me

One way of decreasing the leakage current is increasing the
threshold voltages of transistors. There are several ways to do this,
but in all of them some process technology modification is
necessary. However, this may not be always possible. Another
approach is to use high-threshold voltage devices on non-critical
paths so as to reduce the leakage power while using low-threshold
devices on critical paths so that the circuit performance is
maintained. This technique requires an algorithm that searches for
the gates where the high-threshold voltage devices can be used.
This technique has been called the Dual Vth CMOS.

leakage power categorized under static power consumption. actually for static power consumption there are subthreshold leakage, reverse-bias diode junction leakage, oxide tunneling current, gate induced drain leakage, and channel punch through current. for circuit design, mostly we will deal with subthreshold current. from power formula, P=IV, obviously we can reduce power by reducing Vdd. but the trade-off is delay. one way to reduce subthreshold current by using Multi Vth. Alternatively, you can used stacking method.

*static power will dominate on chip power consumption - ITRS

ananish said:
you can adjust the Vth values from the model file u r using .

as i know, we can adjust Vth by change bulk voltage. normally bulk nmos connected to ground, pmos connected to Vdd. so, chage these connections to other voltage source. for your information, Vsb (bulk voltage) is the function of Vth.

do good partition for main power and resume power, turn off the main power, must take care
for signal between two power domain!!

hi frnds,,,

I have committed a project title for my this month in a project center.. But they said dat dey cant help.. the topic is Effectiveness analysis of low power technique of dynamic logic under temperauture and processs variations. In this dual threshold vge technique is used and leakage power is analysed.. Am having orcad cadence software with me.. but i don knw how to work in dat software.. i ll attach my basepaper with this mail.. Pls give me idea in which tool i hav to analyse leakage power and delay.. Am having very less time to submit.. pls help me.... ill be very thankful if u respond asap...


  • basepaper.pdf
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