Feb 1, 2018 #1 M msdarvishi Full Member level 4 Joined Jul 30, 2013 Messages 230 Helped 1 Reputation 2 Reaction score 1 Trophy points 18 Activity points 2,349 Dear all, I have a question that I would sincerely appreciate if someone can provide me a good and resonable definition of that. We know that we can extract the critical paths in any FPGA design. My question is that: "What is the difference between "Standard Path Delays" and "Critical Path Delays" in an FPGA design?? Kind replies and help are in advance appreciated. Regards,
Dear all, I have a question that I would sincerely appreciate if someone can provide me a good and resonable definition of that. We know that we can extract the critical paths in any FPGA design. My question is that: "What is the difference between "Standard Path Delays" and "Critical Path Delays" in an FPGA design?? Kind replies and help are in advance appreciated. Regards,
Feb 1, 2018 #2 ads-ee Super Moderator Staff member Joined Sep 10, 2013 Messages 7,944 Helped 1,822 Reputation 3,654 Reaction score 1,808 Trophy points 1,393 Location USA Activity points 60,207 critical paths are the ones that are the most likely to fail timing due to excessive number of LUTs between register to register paths. The other paths aren't critical.
critical paths are the ones that are the most likely to fail timing due to excessive number of LUTs between register to register paths. The other paths aren't critical.