Standard Cell Library design

[gopi_vlsi]

Hi-Active Latch with Asyncnous Lo-Active Reset Digital Standard Cell Characterization
can we use transimission gate in a standard cell design ?
and what are the advantages on nand gate based logic ?


the above schematic represents Latch with Asyncnous Lo-Active Reset using transmission gate help me ..


thanks in advance

 

[artmalik]

Transimission gates are used quite often in the standard cell. there is nothing special about them, then are used for complementary signals. As both nmos/pmos are used to transfer signal the sizing can be smaller than required. You can design a mux with and without transmission gate. The sizing will different in each of them.

The disadvantage of transmission gate is routing. the nmos and pmos terminals have to be connected so it makes it difficult. In lower technologies 28nm and beyond the designs are easier to layout without transmission gates.

 

[gopi_vlsi]

thank you artmalik.
as the design is for 90nm library. do my design have specific advantage over NAND gate based design?

thanks.

 

[artmalik]

yeah the advantage in 90nm is that you have relaxed layout rules for poly/metal so you can make the layout compact using transimission gates. In 90nm till 45nm i have used transimission gates without any issues. only beyond that tranmission gates become a nuisance and area intensive due to layout rules. For higher strength cells for performance it makes sense to use transmission gates.