gopi_vlsi
Junior Member level 1
Hi-Active Latch with Asyncnous Lo-Active Reset Digital Standard Cell Characterization
can we use transimission gate in a standard cell design ?
and what are the advantages on nand gate based logic ?
the above schematic represents Latch with Asyncnous Lo-Active Reset using transmission gate help me ..
thanks in advance
can we use transimission gate in a standard cell design ?
and what are the advantages on nand gate based logic ?
the above schematic represents Latch with Asyncnous Lo-Active Reset using transmission gate help me ..
thanks in advance