[SOLVED] Standard Cell Characterization

[VLSICAD]

I am simulating the calibre extracted view of faraday standard cell (0.13um fscoh_d) in cadence and getting the delay and leakage power numbers. these numbers are not at all matching with the given numbers in library. Can anyone please help me and tell me why this is happening?? I have simulated around 5 cells in different corners and getting same results.
Observation: Getting Leakage power more and delay less than given in library. these discripencies are having mor than 100% devaition.

 

[oratie]

First of all, check that the same spice model (transistor model) is the same used for library characterization and for your simulation. The library vendor usually notes the name and version of spice model in the datasheet (or release notes) doc.

 

[VLSICAD]

In the library they have mentioned that they are using the same UMC transistors what I am using in simulation. The transistor model is BSIM-3V3.

 

[VLSICAD]

I got the problem. I extracted the schematic from the spice netlist file of standard cells given by library. Here I did not take care of source/drain area and periphery because of this I was getting this much difference in delay and power. Now I have solved it..