Re: stability of a system
The easiest will be to put a capacitor there, sweep it's value and find out for which value you get good phase margin. More appropriate would be to do some analysis, so you know what's happening in the circuit. If Cc is your capacitor between gate and drain of the PMOS device then the equivalent Miller capacitance at the output of the first stage is approximately CM=gmp*R7*Cc. At the output of the 1st stage you have a dominant pole 1/Ro1(C1+CM) where Ro1 is the output resistance of the 1st stage and C1 is the capacitance (not including the Miller one) at that output. The DC gain is gm1*Ro1*gm2*R7. The unity gain frequency is ωo=gm1*gmp*R7/(C1+gmp*R7*Cc)≈gm1/Cc. The approximate result is if you can assume C1<<CM.
The second pole very approximately is 1/[(R7||(1/gmp))*CL]≈gmp/CL if 1/gmp<<R7. More accurately, but still not exact is
[(R7/gmp)/(R7+(1/gmp)*(C1+Cc)/Cc)]*(C1+CL+CL*C1/Cc)
The zero is approximately gmp/Cc.
If you don't have other restrictions like noise for example, choose your second pole to be 3-4 times higher than the unity gain frequency ωo. The RHP zero is good to be about 10x higher than the ωo, but it is difficult to make. That's why put a resistor in series with Cc to move the zero to ∞ or in the LHP close to the second pole, which will kind of cancel it. Be aware though that this cancellation is not a good idea if your circuit is processing pulse or step-like signals where you need good and fast settling. It is ok for sin signals. You can find in books the formula for this resistor or just sweep it's value until you get satisfactory results.