stability of a feedback loop in a digital driver

[mburakbaran]

Hello, I am designing a slew-rate controlled digital output driver. The simplified output stage is attached. The feedback is done via the capacitor at the picture from output to a switching nodes. You can see the two switch transistors in rectangular.

Here, I am also adding series resistors to the gates of the output transistors in order to filter out some EMI that might be coupled inside. The output transistors are pretty big (around 5mm width fro the pmos e.g.) so adding a series resistor basically forms a Low pass RC. Anyway, my question is, how can I analyze the stability of these two feedback loops shown in circles? I mean I am doing transient simulations and all and everything seems ok, but what should I do to make sure that this will operate stable? I do not know about cutting the loops and applying sth from somewhere and stuff. Could somebody be help with this?

Much appreciated and thanks a lot.

 

[erikl]

You didn't reveal which analysis tool you're using. If it is Cādence SPECTRE, insert an iprobe instance in series with C_f, run an STB analysis and plot gain & phase.

 

[mburakbaran]

You didn't reveal which analysis tool you're using. If it is Cādence SPECTRE, insert an iprobe instance in series with C_f, run an STB analysis and plot gain & phase.

Hello,

I am indeed using Cadence. I have put the iprobe instance in series with the cap but Where should I examine the gain and phase? I mean which two points should those be to select when choosing gain&phase? I am a little confused. If it was an opamp, i would have looked to the gain and phase between output and the input, but here, since this is a digital circuit, it is probably solving for one of the output transistors off case (either logic 1 or 0) considering that specific DC point. Am I making any sense? Thanks a lot.

 

[erikl]

Right, it's always between input and output, however I'm not sure if this would work successfully with sort of a digital circuit. But you could try it anyway, separately for both logic states.

Another possibility would be PSTB, see this SpectreRF PSTB Analysis Application Note.