This is the usual "box" that LDO designers live in.
Your final stage's sizing has no choice but to support
the Iout(max)@Vdropout(max). The gate drive has to
deal. You also need to be sure that the gate drive is
not "winding up" from a still-too-small output FET. If
it does then you will see relaxation oscillations. The
character of oscillation is a clue for you - small signal
sinusoidal, or large signal sawtooth, point to different
issues and solutions.
At some point you may need to add circuitry that
either changes the compensation based on load (which
is a proxy for Zout in small signal) or changes the Zout
to enforce a minimum Zout, higher corner frequency at
low load. As with the max load case, min load can make
the gate driver "wind up", this time against the positive
rail (trying to get drain current to zero, which can never
happen - microamps, maybe, depending on technology
and device size, temp and line, etc.).
You might also "negotiate" a solution; if the min load can
be predicted and agreed upon, maybe you get relief on
the min current for in-regulation accuracy, and ease the
range of Zout you have to accommodate.