Stability LDO with high output currents

[Zena356]

Hi!

I try to design Low Drop Out regulator (LDO) circuit with load current up to 1.5 A, with Cload about 10µF. and Resr ~ 0.1 - 5 Ω
But I was faced with the problem of stability. With such large output currents, a large output transistor is required, respectively, a large parasitic gate capacitance. Stability is obtained at high currents of 100mA. At low currents, the phase margin is below 30 degrees. Do you know any methods of compensation for this circuit in a wide range of currents?

thank you in advance

 

[frankrose]

Depends on the circuit there could be more solutions, show your schematic please. Not only one kind of LDO exist.

 

[dick_freebird]

This is the usual "box" that LDO designers live in.

Your final stage's sizing has no choice but to support
the Iout(max)@Vdropout(max). The gate drive has to
deal. You also need to be sure that the gate drive is
not "winding up" from a still-too-small output FET. If
it does then you will see relaxation oscillations. The
character of oscillation is a clue for you - small signal
sinusoidal, or large signal sawtooth, point to different
issues and solutions.

At some point you may need to add circuitry that
either changes the compensation based on load (which
is a proxy for Zout in small signal) or changes the Zout
to enforce a minimum Zout, higher corner frequency at
low load. As with the max load case, min load can make
the gate driver "wind up", this time against the positive
rail (trying to get drain current to zero, which can never
happen - microamps, maybe, depending on technology
and device size, temp and line, etc.).

You might also "negotiate" a solution; if the min load can
be predicted and agreed upon, maybe you get relief on
the min current for in-regulation accuracy, and ease the
range of Zout you have to accommodate.

 

[Zena356]

I tried differents tyes. One of this contains: 2 stage amplifier, in which first provides the required loop gain and bandwidth and another one is devised to promote the transient response. Moreover, it contains Bias circuit, which provides bias currents depending on load current. Block diagram attached below:

 

[frankrose]

How the A and B amplifiers and the current limit look like? Do you know these transfer function? We should get every useful imformation about your circuit. I guess at lower currents a right-half plane zero can occur because of the decreased transconductance of the output FET, but without Bode plots, exact circuit and your target specifications hard to answer.
How much is the minimum load where phase margin is 60 degrees yet? Can't you just decrease the RF1 and RF2 to ensure the stability? Would be simple solution.