ramesh28
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hello all,
i have doubt regarding, how all data from fast clock to slow clock path recivced correctly at capture flop?
suppose clock period of fast clock = 10ns and slow clock = 25ns then in that case launch clock is fast clock and capture clock is slow clock.
i think data of some edges from launch clock may not captured by capture clock? is that right?
If is there any method to handle this case? then please suggest.
for slow clock to fast clock path, we can consider multicycle path case so that there is no chance for data loss but here in case of fast clock to slow clock path, i'm little bit confused. how this path handled without data loss..?
thank you..
i have doubt regarding, how all data from fast clock to slow clock path recivced correctly at capture flop?
suppose clock period of fast clock = 10ns and slow clock = 25ns then in that case launch clock is fast clock and capture clock is slow clock.
i think data of some edges from launch clock may not captured by capture clock? is that right?
If is there any method to handle this case? then please suggest.
for slow clock to fast clock path, we can consider multicycle path case so that there is no chance for data loss but here in case of fast clock to slow clock path, i'm little bit confused. how this path handled without data loss..?
thank you..