[STA] Clock Uncertancy -> what values should be used?

[ivlsi]

Hi All,

Is there a thumb rule what values should be used for the clock uncertainty?

Let's say, will 20% of clock period for the setup checks and 5% for the hold checks be good enough?

Thank you!

 

[artmalik]

This information is mainly determined by the PLL design which is a source of clock jitter(uncertainty). it is dependant on the clock speed as well depth of the clock. I don't think there is any "rule of thumb" as it is very design specific.