STA + Asynchronous Design + multiclock domains

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ivlsi

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Hi All,

How Asynchronous Designs with the multi-clock asynchronous domains should be checked in STA tools?

Thank you!
 

First set the path as false path between the clock domains.

Then
1. If there is no data going through between these clocks then fine no problem. U can carry on with the STA.
2. If not then u need to have FIFO design with sufficient depth, so that there r no data lost. Which is normally written in the verilog code itself by the coding team.
 
should multi-cycle constrains be put on the synchronizers?
 

Do we use STA for asynchronous designs ?? if i remember properly , STA is evaluated for synch. designs only , for Asynch. designs DTA is used.

Correct me if i am wrong.
 

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