Our medothology is to analyze all pvt we have to cover as possible the design for hold and setup.
For clock / data paths, you could have differentiate rating to graded more margins.
My take away from the above mentioned link is that interconnect delay(mainly due to metal wires) varies differently than resistance/capacitance of transistor device. So worst corner timing library with certaint PVT may not be worst for both interconnect and transistor devices. We need to do analysis in all combination of corners for RC interconnect delay and timing library to account for all variations. Total combination for single mode and 3 corners are 9(rc best-lib best, rc best-lib worst, ...and so on). Nowadays, chips operate in more than a single mode . For example if there is a functional and a test mode in a chip. The total combination for timing analysis will be 18. These kind of timing analysis are called mutli mode multi corner (MMMC) timing analysis.