[STA] Analysis Corners - how many do exist?

[ivlsi]

Hello All,

How many Analysis Corners do exist/used for the Static Timing Analysis?

Are the Best Case, Worst Case and Typical Case the corners?

How can I analyze the max delays on the data path versus the min delays on the clock tree paths?

Thank you!

 

[rca]

Our medothology is to analyze all pvt we have to cover as possible the design for hold and setup.
For clock / data paths, you could have differentiate rating to graded more margins.

 

[ivlsi]

Our methodology is to analyze all pvt

Okay, so how many do exist? WC, BC, TC - are there others? Is there a sense to run STA for the Typical delays (TC)?

What about OCV (OnChip Variations) analysis? How should it be performed?

For clock / data paths, you could have differentiate rating to graded more margins

How can I do that practically? What's the flow? settings? commands?

Thank you!

 

[rca]

I don't talk any more of WC-BC, I check all PVT so I will cover WC-BC also.
we add 5 to 8 % on clock derate and also in data derate.

 

[birdy123]

Hello All,

How many Analysis Corners do exist/used for the Static Timing Analysis?

Are the Best Case, Worst Case and Typical Case the corners?

How can I analyze the max delays on the data path versus the min delays on the clock tree paths?

Thank you!

Please check the following links it might Help you. A lot of basics are required.. Still Worth reading these articles.

**broken link removed**
**broken link removed**
**broken link removed**

---------- Post added at 16:03 ---------- Previous post was at 16:01 ----------

Hi dmitryl,

Looka like you already have similar type of question but in different way.

 

[ivlsi]

birdy123,
links, which you provided, are broken.... Could you please provide the valid links?
Thank you!

 

[tariq786]

**broken link removed**
**broken link removed**
**broken link removed**

These dont work

Please specify complete urls

 

[birdy123]

Hi,
Don't know what's the problem ... anyway .. links are

Parasitic Interconnect Corner RC model

Design Constraint Maximum Transition



let me know if it works..

---------- Post added at 10:03 ---------- Previous post was at 09:52 ----------

another Link is ...

Process variation Effects on design

 

[morris_mano]

My take away from the above mentioned link is that interconnect delay(mainly due to metal wires) varies differently than resistance/capacitance of transistor device. So worst corner timing library with certaint PVT may not be worst for both interconnect and transistor devices. We need to do analysis in all combination of corners for RC interconnect delay and timing library to account for all variations. Total combination for single mode and 3 corners are 9(rc best-lib best, rc best-lib worst, ...and so on). Nowadays, chips operate in more than a single mode . For example if there is a functional and a test mode in a chip. The total combination for timing analysis will be 18. These kind of timing analysis are called mutli mode multi corner (MMMC) timing analysis.