You're confused because you think that if you have a 1024-words SRAM containing 32 bits, then the memory cut is organized in 1024 rows by 32 columns
But that would mean creating very bad aspect ratio (longest length/shortest length) memory instances in your design. It would be hard to use such a memory where some memory words would take too much time to be read
So basically you can use a MUX4 ratio and build a 256 rows by 128 columns design, interleaving data of 4 32-bit words in a single 128 bit physical row. You then need a 4-2-1 MUX or column selector to decide if you want the 1st, 2nd, 3rd or 4th word out from the 4 words compacted in the single physical row
@Clorindo this is what i as not able to understand even though read so many article.
you have given perfect answer . i am implementing it in cadence , still i have some queries. i will ask later
in the attachment i have drawn SRAM bit cell and only 1 word 32 colunm, for which i have taken 5:32 decoder.
Now as you know that for row decoder , the output of row decoder is connected to the word line wire of 6T bit cell. But where will be the output of column decoder will goes (suppose i select 1st column of word1). Because the wires BL and BL are connected to the write driver . Can you please answer this. i am confused that where we have to connect the output to select particular column of word 1 (say).
@dick_freebird .My ques is where the output of Column decoder will goes to the particular selected column. so that the particular column is get activated (like to activate the row the word line is given to gate of pass transistors of bit cell
It's been a good while since I messed with SRAM guts but people
show me pictures. I expect the outboard S/D of your row pass FETs
go to column (call them C# and C#b) which are precharged ahead
of row apply, the cell now jacks the (should be nulled) C# and C#b
apart, sense amp senses and bing badda boom.
Or something like that. Maybe there's something new.