SRAM

[parminder]

Why do we need a column decoder and mux in SRAM?

Hi, i am bit confused that once we select particular rom and column that why mux is required?

 

[KlausST]

Hi,

This is a bit of general question without context.

To understand your worries, could you please draw a sketch, or refer to an internet site?

And what's your idea? How could an alternative look like?

Klaus

 

[parminder]

here you can see that there are writing both MUX and decoder . can you first explain it then i will ask further doubt

reference : GOOGLE

 

[KlausST]

Hi,

you did not answer about your idea.
How can it work without decoder? Or, how can it work without MUX?
Which one do you think one can omit?

reference : GOOGLE

I get many million hits on GOOGLE. --> I don´t spend the time to look for your source.

Klaus

 

[Clorindo]

Hi @parminder,

You're confused because you think that if you have a 1024-words SRAM containing 32 bits, then the memory cut is organized in 1024 rows by 32 columns

But that would mean creating very bad aspect ratio (longest length/shortest length) memory instances in your design. It would be hard to use such a memory where some memory words would take too much time to be read

So basically you can use a MUX4 ratio and build a 256 rows by 128 columns design, interleaving data of 4 32-bit words in a single 128 bit physical row. You then need a 4-2-1 MUX or column selector to decide if you want the 1st, 2nd, 3rd or 4th word out from the 4 words compacted in the single physical row

Best regards,
L

 

[parminder]

@Clorindo this is what i as not able to understand even though read so many article.
you have given perfect answer . i am implementing it in cadence , still i have some queries. i will ask later