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You're confused because you think that if you have a 1024-words SRAM containing 32 bits, then the memory cut is organized in 1024 rows by 32 columns
But that would mean creating very bad aspect ratio (longest length/shortest length) memory instances in your design. It would be hard to use such a memory where some memory words would take too much time to be read
So basically you can use a MUX4 ratio and build a 256 rows by 128 columns design, interleaving data of 4 32-bit words in a single 128 bit physical row. You then need a 4-2-1 MUX or column selector to decide if you want the 1st, 2nd, 3rd or 4th word out from the 4 words compacted in the single physical row