The problem of a large difference between post-layout circuit simulation and schematic simulation is a very common one.
The usual process to debug this is to find out what parasitic elements are the most critical, in destroying your nice (schematic) circuit behavior.
I would suggest to do R-only extraction, and see if your circuit behaves well, or not.
Next, try to imagine, to envision (or to simulate) what would be a potential impact of various parasitics on your circuit misbehavior - such as IR drop on bias lines, or large delay, or mismatch between nets, etc.
You can insert presistor and pcapacitor elements into your schematic, with values corresponding to extracted parasitics, and see what happens, which of them deteriorates your circuit behavior.
Things to look at, are port to device or device to device effective (parasitic resistance), RC delay, coupling between nets, mismatch (capacitive or resistive) in your sense amplifier, etc.
In general, for slow / low performance circuits, and in older technology nodes, parasitics is usually a smaller problem, and becomes much more important for advanced nodes (let's say 20nm and below), and/or for high-speed circuits.