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Sram bit cell design: Fom definitions

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maktoomi

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Hello everyone,

In order to evaluate Figure of Merit(FOM) of a 6T-SRAM bit cell using spice, i need to first understand various FOMs.
So, how do we define technically for a 6T-sram:
(1) write margin
(2) Leakage power
(3) Cell current
(4) Bit line leakage
(5) Discharge rate
(6) Write time
(7) Retention voltage

(Wherever possible kindly also mention the voltage levels of Bit/word lines while defining FOMs. Also, SNM is intentionally not mentioned as i was able to determine it).

Thanks.
 

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