SR latch- VHDL code. Please help.

[delon]

Hello, I am a beginner in VHDL. I wrote a code for gated SR latch which is mentioned bellow:

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY hw IS
PORT ( ck, s, r : IN std_logic;
q, qnot : BUFFER std_logic);
END hw;

ARCHITECTURE sr OF hw IS

BEGIN
PROCESS (ck,s,r) BEGIN
IF ( ck ='1' AND r='1' AND s='0') THEN
q <='0';
qnot<= NOT q;
ELSIF ( ck ='1' AND r='0' and s='1') THEN
q <='1';
qnot<= NOT q;
ELSIF ( ck ='1' AND r='1' and s='1') THEN
q <='X';
qnot<= 'X';
END IF;
END PROCESS;

END sr;

I run this code as a functional simulation in Altera Quartus II. In the simulation result, I am not getting 'X' for s=r=1 input combination. Here is a screenshot:

For s=1, r=1, I am getting '0' in q. Does it mean that, the PROCESS is not evaluating the condition when s or r changes it's value? What might be the reason for that. Please help.

 

[TrickyDicky]

the quartus simulator does a post place and route simulation, so 'X' is not a valid output. for 'X' you need to use modelsim. quartus converts your code to actual logic.

just a note, this is not a valid Sr latch description. I suggest you have a look at the quartus coding guidelines.

 

[delon]

Thanks for your response. It make sense. But what do mean "this is not a valid Sr latch description"? Would you please give me a little more hint ?

 

[TrickyDicky]

you have not used the correct synchronous template, so it is not synchronous. it is just a load of logic, and the output can change whenever the click is high rather than on the rising edge of the clock.

this is the standard template.

process(clk, async_reset)
begin
  if async_reset = '1' then 
    --do asynchronous reset

  elsif rising_edge(clk) then
    -- put sync stuff here

  end if;
end process;