SR flip flop design in Ltspice

[rahul.6sept]

Hi,
I'm trying to design a clocked SR flip-flop in Ltspice with a pulsed voltage source. I set the time step 100 ms. When I run it gives an error "Time step too small". I increased the time step but it does not solve the issue. Please advice me a solution to it. Attached herewith my circuit.

 

[dick_freebird]

What are you calling a "clocked SR"? Those don't really go together. A JK FF is sorta like that. A SR FF is asynchronous.

100ms is pretty large for low voltage logic (and about anything else) as a.timestep.

Bistable logic wants an initialization. The "R" state asserted at DC maybe. But by im0osing a clock you may defeat any reset unless an async reset path is added.

 

[FvM]

Wrong circuit. A2 and A4 have inverting feedback. What do you try to achieve?

--- Updated Jan 1, 2022 ---

Guess you want to model a gated SR latch:

Problem is that it needs an initial condition for the output latch, also it doesn't handle the input condition S=1 and R=1 which causes an undefined output in real hardware.

--- Updated Jan 1, 2022 ---

You can overcome the RS latch race condition by introducing a small asymmetry, e.g. adding a pF load capacitance to one of the outputs.

--- Updated Jan 1, 2022 ---